FPGA hardware primitives are complex; high-level operations which traditionally consisted of many low-level gates can now be implemented with single units such as digital signal processors (DSPs). These units are powerful because they can be programmed to implement specific behaviors. However, taking full advantage of this programmabilty is difficult. FPGA synthesis tools were originally built to support architectures consisting only of simple primitives such as lookup tables (LUTs). As a result, these tools lack the capability to fully reason about the behavior of complex units like DSPs. This directly affects the quality of compiled designs, as failure to map an eligible design to DSPs can result in orders of magnitude of performance degradation. In this paper, we explore the limitations of current tools with regard to complex primitives—specifically, the Xilinx UltraScale+ DSP48E2. We conduct a survey of FPGA synthesis tools targeting the DSP48E2, attempting to map a number of common designs onto the DSP using each tool. We present a number of simple designs which existing state of the art tools fail to map, highlighting these tools’ inability to completely reason about complex primitives.