ICFP 2023
Mon 4 - Sat 9 September 2023 Seattle, Washington, United States

FPGA technology mapping is a critical step in hardware compilation; from high-level hardware design descriptions, toolchains must find an equivalent low-level implementation on the target FPGA’s primitives. FPGAs are becoming increasingly heterogeneous via the addition of new, highly configurable primitives with complex behaviors. Effectively utilizing these primitives can produce orders of magnitude better performance, meaning robust technology mapping is more important than ever. Current automated approaches for technology mapping work for simple primitives, but fall short when tasked to map modern complex primitives. This is because configuring these primitives requires tools which can understand and utilize their complex behavior, such as pipelined arithmetic or runtime reconfigurability. Put simply: configuring modern, complex FPGA primitives is equivalent to synthesizing programs. Consequently, ongoing work—Lakeroad—applies program synthesis to address this mapping gap by using semantics extracted from Verilog descriptions of primitives. However, Lakeroad’s compilation flow still requires adding support for new primitives to the tool, and it is unclear whether this approach will be extensible to increasingly diverse complex primitives. In this paper, we identify the CFGLUT5 as a primitive that thoroughly demonstrates the extensibility of Lakeroad while also highlighting the limitations of the approach as of now. CFGLUT5 is a specialized primitive by Xilinx, that has behavior currently unrealized in Lakeroad’s primitive library. The difficulty of mapping to the primitive is evident, as it is not supported by any compiler, including Xilinx’s own proprietary tool-chain Vivado. We show the promise of Lakeroad’s approach by mapping a variety of common operations to CFGLUT5, and elaborate on ongoing work and limitations.